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K4D263238D
128M DDR SDRAM
128Mbit DDR SDRAM
1M x 32Bit x 4 Banks Double Data Rate Synchronous DRAM with Bi-directional Data Strobe and DLL
Revision 1.3 July 2002
-1-
Rev. 1.3 (Jul. 2002)
K4D263238D
Revision History
Revision 1.3 (July 18, 2002)
* Changed power dissipation from 2.0W to 1.8W
128M DDR SDRAM
Revision 1.2 (June 17, 2002)
* Removed K4D263238D-QC55 from the spec. * 183/166MHz were supported in K4D263238D-QC50.
Revision 1.1 (May 24, 2002)
* Removed K4D263238D-QC45/60 from the spec
Revision 1.0 (May 20, 2002)
* Define DC spec.
Revision 0.0 (April 23, 2002)- Target spec
* Define target spec.
-2-
Rev. 1.3 (Jul. 2002)
K4D263238D
128M DDR SDRAM
1M x 32Bit x 4 Banks Double Data Rate Synchronous DRAM with Bi-directional Data Strobe and DLL FEATURES
* 2.5V 5% power supply * SSTL_2 compatible inputs/outputs * 4 banks operation * MRS cycle with address key programs -. Read latency 3,4 (clock) -. Burst length (2, 4, 8 and Full page) -. Burst type (sequential & interleave) * Full page burst length for sequential burst type only * Start address of the full page burst should be even * All inputs except data & DM are sampled at the positive going edge of the system clock * Differential clock input * No Write Interrupted by Read function * Data I/O transactions on both edges of Data strobe * DLL aligns DQ and DQS transitions with Clock transition * Edge aligned data & data strobe output * Center aligned data & data strobe input * DM for write masking only * Auto & Self refresh * 32ms refresh period (4K cycle) * 100pin TQFP package * Maximum clock frequency up to 250MHz * Maximum data rate up to 500Mbps/pin
ORDERING INFORMATION
Part NO. K4D263238D-QC40 K4D263238D-QC50 Max Freq. 250MHz 200MHz Max Data Rate 500Mbps/pin 400Mbps/pin Interface SSTL_2 Package 100 TQFP
GENERAL DESCRIPTION
FOR 1M x 32Bit x 4 Bank DDR SDRAM
The K4D263238D is 134,217,728 bits of hyper synchronous data rate Dynamic RAM organized as 4 x 1,048,576 words by 32 bits, fabricated with SAMSUNGs high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance up to 2.0GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety of high performance memory system applications. -3-
Rev. 1.3 (Jul. 2002)
K4D263238D
PIN CONFIGURATION (Top View)
128M DDR SDRAM
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51 50 49 48 47 46 45 44 43
DQ29 VSSQ DQ30 DQ31 VSS VDDQ N.C N.C N.C N.C N.C VSSQ RFU DQS VDDQ VDD DQ0 DQ1 VSSQ DQ2
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 10 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 11 1 2 3 4 5 6 7 8 9
A8(AP)
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VREF
DQ28
DQ27
DQ26
DQ25
DQ24
DQ15
DQ14
DQ13
DQ12
DQ10
DQ11
VDD
DM3
DM1
CKE
DQ9
DQ8
VSS
CK
CK
MCL
A7 A6 A5 A4 VSS A9 N.C N.C N.C N.C N.C N.C N.C A11 A10 VDD A3 A2 A1 A0
100 Pin TQFP 20 x 14 mm2 0.65mm pin Pitch
42 41 40 39 38 37 36 35 34 33 32 31
VSS
WE
CAS
RAS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM0
DM2
DQ3
DQ4
DQ5
DQ6
DQ7
CS
BA0
VSSQ
VSSQ
VDDQ
VDDQ
VDDQ
VSSQ
PIN DESCRIPTION
CK,CK CKE CS RAS CAS WE DQS DMi RFU Differential Clock Input Clock Enable Chip Select Row Address Strobe Column Address Strobe Write Enable Data Strobe Data Mask Reserved for Future Use BA0, BA1 A0 ~A11 DQ0 ~ DQ31 VDD VSS VDDQ VSSQ MCL Bank Select Address Address Input Data Input/Output Power Ground Power for DQs Ground for DQs Must Connect Low
VDDQ
VDD
-4-
Rev. 1.3 (Jul. 2002)
BA1
K4D263238D
INPUT/OUTPUT FUNCTIONAL DESCRIPTION
Symbol CK, CK*1 Input Type
128M DDR SDRAM
Function The differential system clock Input. All of the inputs are sampled on the rising edge of the clock except DQs and DMs that are sampled on both edges of the DQS. Activates the CK signal when high and deactivates the CK signal when low. By deactivating the clock, CKE low indicates the Power down mode or Self refresh mode. CS enables the command decoder when low and disabled the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. Latches row addresses on the positive going edge of the CK with RAS low. Enables row access & precharge. Latches column addresses on the positive going edge of the CK with CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from CAS, WE active. Data input and output are synchronized with both edge of DQS. Data In mask. Data In is masked by DM Latency=0 when DM is high in burst write. DM0 for DQ0 ~ DQ7, DM1 for DQ8 ~ DQ15, DM2 for DQ16 ~ DQ23, DM3 for DQ24 ~ DQ31. Data inputs/Outputs are multiplexed on the same pins. Selects which bank is to be active. Row/Column addresses are multiplexed on the same pins. Row addresses : RA0 ~ RA11, Column addresses : CA0 ~ CA7. Column address CA8 is used for auto precharge. Power and ground for the input buffers and core logic. Isolated power supply and ground for the output buffers to provide improved noise immunity. Reference voltage for inputs, used for SSTL interface. Must connect Low
CKE
Input
CS
Input
RAS CAS WE DQS DM0 ~ DM3 DQ0 ~ DQ31 BA0, BA1 A0 ~ A11 VDD/VSS VDDQ/VSSQ VREF MCL
Input Input Input Input/Output Input Input/Output Input Input Power Supply Power Supply Power Supply Must Connect Low
*1 : The timing reference point for the differential clocking is the cross point of CK and CK. For any applications using the single ended clocking, apply VREF to CK pin.
-5-
Rev. 1.3 (Jul. 2002)
K4D263238D
BLOCK DIAGRAM (1Mbit x 32I/O x 4 Bank)
128M DDR SDRAM
32
Intput Buffer I/O Control LWE LDMi
CK, CK Bank Select
Data Input Register Serial to parallel
64
1Mx32 Output Buffer 2-bit prefetch Sense AMP Refresh Counter Row Buffer Row Decoder 1Mx32 1Mx32 1Mx32
64 32
x32
DQi
Address Register
CK,CK ADDR
Column Decoder LRAS LCBR Col. Buffer
Latency & Burst Length Strobe Gen. Data Strobe
Programming Register LCKE LRAS LCBR LWE LCAS LWCBR
DLL
CK,CK
LDMi
Timing Register
CK,CK
CKE
CS
RAS
CAS
WE
DMi
-6-
Rev. 1.3 (Jul. 2002)
K4D263238D
FUNCTIONAL DESCRIPTION
* Power-Up Sequence
128M DDR SDRAM
DDR SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. 1. Apply power and keep CKE at low state (All other inputs may be undefined) - Apply VDD before VDDQ . - Apply VDDQ before VREF & VTT 2. Start clock and maintain stable condition for minimum 200us. 3. The minimum of 200us after stable power and clock(CK,CK ), apply NOP and take CKE to be high. 4. Issue precharge command for all banks of the device. 5. Issue a EMRS command to enable DLL *1 6. Issue a MRS command to reset DLL. The additional 200 clock cycles are required to lock the DLL. *1,2 7. Issue precharge command for all banks of the device. 8. Issue at least 2 or more auto-refresh commands. 9. Issue a mode register set command with A8 to low to initialize the mode register. *1 The additional 200cycles of clock input is required to lock the DLL after enabling DLL. *2 Sequence of 6&7 is regardless of the order.
Power up & Initialization Sequence
0 CK CK
tRP
2 Clock min. 2 Clock min.
precharge ALL Banks
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

Command
precharge ALL Banks
EMRS
MRS DLL Reset
1st Auto Refresh
2nd Auto Refresh
tRP
tRFC
tRFC
2 Clock min.
Mode
Register Set
Any Command
Inputs must be stable for 200us

200 Clock min.
-7-
Rev. 1.3 (Jul. 2002)
K4D263238D
MODE REGISTER SET(MRS)
128M DDR SDRAM
The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency, addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after EMRS setting for proper operation. The mode register is written by asserting low on CS, RAS, CAS and WE(The DDR SDRAM should be in active mode with CKE already high prior to writing into the mode register). The state of address pins A0 ~ A11 and BA0, BA1 in the same cycle as CS, RAS, CAS and WE going low is written in the mode register. Minimum two clock cycles are requested to complete the write operation in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. The mode register is divided into various fields depending on functionality. The burst length uses A0 ~ A2, addressing mode uses A3, CAS latency(read latency from column address) uses A4 ~ A6. A7 is used for test mode. A8 is used for DLL reset. A7,A8, BA0 and BA1 must be set to low for normal MRS operation. Refer to the table for specific codes for various burst length, addressing modes and CAS latencies. BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus Mode Register
RFU
0
RFU
DLL
TM
CAS Latency
BT
Burst Length
Burst Type DLL A8 0 1 DLL Reset No Yes Test Mode A7 0 1 mode Normal Test Burst Length CAS Latency BA0 0 1 An ~ A0 MRS EMRS A6 0 0 0 0 * RFU(Reserved for future use) should stay "0" during MRS cycle. 1 1 1 1 MRS Cycle
0 CK, CK Command
NOP Precharge All Banks NOP NOP MRS NOP Any Command NOP NOP
A3 0 1
Type Sequential Interleave
A2 Latency Reserved Reserved Reserved 3 4 Reserved Reserved Reserved 0 0 0 0 1 1 1 1
A1 0 0 1 1 0 0 1 1
A0 0 1 0 1 0 1 0 1
Burst Type Sequential Reserve 2 4 8 Reserve Reserve Reserve Full page Interleave Reserve 2 4 8 Reserve Reserve Reserve Reserve
A5 0 0 1 1 0 0 1 1
A4 0 1 0 1 0 1 0 1
1
2
3
4
5
6
7
8
tRP
tMRD=2 tCK
*1: MRS can be issued only at all banks precharge state. *2: Minimum tRP is required to issue MRS command. -8-
Rev. 1.3 (Jul. 2002)
K4D263238D
EXTENDED MODE REGISTER SET(EMRS)
128M DDR SDRAM
The extended mode register stores the data for enabling or disabling DLL and selecting output driver strength. The default value of the extended mode register is not defined, therefore the extend mode register must be written after power up for enabling or disabling DLL. The extended mode register is written by asserting low on CS, RAS, CAS, WE and high on BA0(The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register). The state of address pins A0, A2 ~ A5, A7 ~ A11 and BA1 in the same cycle as CS, RAS, CAS and WE going low are written in the extended mode register. A1 and A6 are used for setting driver strength to weak or matched impedance. Two clock cycles are required to complete the write operation in the extended mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. A0 is used for DLL enable or disable. "High" on BA0 is used for EMRS. All the other address pins except A0,A1,A6 and BA0 must be set to low for proper EMRS operation. Refer to the table for specific codes.
BA1
BA0
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address Bus Extended Mode Register
RFU
1
RFU
D.I.C
RFU
D.I.C
DLL
BA0 0 1
An ~ A0 MRS EMRS
A6 0 1
A1 1 1
Output Driver Impedance Control Weak Matched
A0 0 1
DLL Enable Enable Disable
* RFU(Reserved for future use) should stay "0" during EMRS cycle.
Figure 7. Extend Mode Register set
-9-
Rev. 1.3 (Jul. 2002)
K4D263238D
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to Vss Voltage on VDD supply relative to Vss Voltage on VDD supply relative to Vss Storage temperature Power dissipation Short circuit current Symbol VIN, VOUT VDD VDDQ TSTG PD IOS Value
128M DDR SDRAM
Unit V V V C W mA
-0.5 ~ 3.6 -1.0 ~ 3.6 -0.5 ~ 3.6 -55 ~ +150 1.8 50
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
POWER & DC OPERATING CONDITIONS(SSTL_2 In/Out)
Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 65C)
Parameter
Device Supply voltage Output Supply voltage Reference voltage Termination voltage Input logic high voltage Input logic low voltage Output logic high voltage Output logic low voltage Input leakage current Output leakage current
Symbol
VDD VDDQ VREF Vtt VIH VIL VOH VOL IIL IOL
Min
2.375 2.375 0.49*VDDQ VREF-0.04 VREF+0.15 -0.30 Vtt+0.76 -5 -5
Typ
2.50 2.50 VREF -
Max
2.625 2.625 0.51*VDDQ VREF+0.04 VDDQ+0.30 VREF-0.15 Vtt-0.76 5 5
Unit
V V V V V V V V uA uA
Note
1 1 2 3 4 5 IOH=-15.2mA IOL=+15.2mA 6 6
Note : 1. Under all conditions VDDQ must be less than or equal to VDD. 2. VREF is expected to equal 0.50*VDDQ of the transmitting device and to track variations in the DC level of the same. Peak to peak noise on the VREF may not exceed + 2% of the DC value. Thus, from 0.50*VDDQ, VREF is allowed + 25mV for DC error and an additional + 25mV for AC noise. 3. Vtt of the transmitting device must track VREF of the receiving device. 4. VIH(max.)= VDDQ +1.5V for a pulse and it which can not be greater than 1/3 of the cycle rate. 5. VIL(min.)= -1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate. 6. For any pin under test input of 0V VIN VDD is acceptable. For all other pins that are not under test VIN=0V.
- 10 -
Rev. 1.3 (Jul. 2002)
K4D263238D
DC CHARACTERISTICS
Recommended operating conditions Unless Otherwise Noted, TA=0 to 65C)
128M DDR SDRAM
Version Parameter Operating Current (One Bank Active) Precharge Standby Current in Power-down mode Precharge Standby Current in Non Power-down mode Active Standby Current power-down mode Active Standby Current in in Non Power-down mode Operating Current ( Burst Mode) Refresh Current Self Refresh Current Symbol Test Condition -40 ICC1 ICC2P ICC2N ICC3P ICC3N ICC4 ICC5 ICC6 Burst Lenth=2 tRC tRC(min) -50 215 60 90 80 150 530 230 3
Unit
Note
IOL=0mA, tCC= tCC(min)
CKE VIL(max), tCC= tCC(min) CKE VIH(min), CS VIH(min),
245 70 100 100 175 630 250
mA mA mA mA mA mA mA mA
1
tCC= tCC(min).
CKE VIL(max), tCC= tCC(min) CKE VIH(min), CS VIH(min),
tCC= tCC(min) .
IOL=0mA ,tCC= tCC(min), Page Burst, All Banks activated.
tRC tRFC(min)
CKE 0.2V
2
Note: 1. Measured with outputs open. 2. Refresh period is 32ms.
AC INPUT OPERATING CONDITIONS
Recommended operating conditions(Voltage referenced to VSS=0V, VDD/ VDDQ=2.5V+ 5%, TA=0 to 65C)
Parameter
Input High (Logic 1) Voltage; DQ Input Low (Logic 0) Voltage; DQ Clock Input Differential Voltage; CK and CK Clock Input Crossing Point Voltage; CK and CK
Symbol
VIH VIL VID VIX
Min
VREF+0.35 0.7 0.5*VDDQ-0.2
Typ
-
Max
VREF-0.35 VDDQ+0.6 0.5*VDDQ+0.2
Unit
V V V V
Note
1 2
Note : 1. VID is the magnitude of the difference between the input level on CK and the input level on CK 2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same
- 11 -
Rev. 1.3 (Jul. 2002)
K4D263238D
128M DDR SDRAM
AC OPERATING TEST CONDITIONS (VDD/ VDDQ=2.5V+ 5% , TA= 0 to 65C)
Parameter Input reference voltage for CK(for single ended) CK and CK signal maximum peak swing CK signal minimum slew rate Input Levels(VIH/VIL) Input timing measurement reference level Output timing measurement reference level Output load condition Value 0.50*VDDQ 1.5 1.0 VREF+0.35/VREF-0.35 VREF Vtt See Fig.1 Unit V V V/ns V V V Note
Vtt=0.5*VDDQ
RT=50 Output Z0=50 CLOAD=30pF
VREF =0.5*VDDQ
(Fig. 1) Output Load Circuit
CAPACITANCE (VDD=2.5V, TA= 25C, f=1MHz)
Parameter
Input capacitance( CK, CK ) Input capacitance(A0~A10, BA0~BA1) Input capacitance ( CKE, CS, RAS,CAS, WE ) Data & DQS input/output capacitance(DQ0~DQ31) Input capacitance(DM0 ~ DM3)
Symbol
CIN1 CIN2 CIN3 COUT CIN4
Min
1.0 1.0 1.0 1.0 1.0
Max
5.0 4.0 4.0 6.0 6.0
Unit
pF pF pF pF pF
DECOUPLING CAPACITANCE GUIDE LINE
Recommended decoupling capacitance added to power line at board. Parameter Decoupling Capacitance between VDD and VSS Decoupling Capacitance between VDDQ and VSSQ Symbol CDC1 CDC2 Value 0.1 + 0.01 0.1 + 0.01 Unit uF uF
Note : 1. VDD and VDDQ pins are separated each other. All VDD pins are connected in chip. All VDDQ pins are connected in chip. 2. VSS and VSSQ pins are separated each other All VSS pins are connected in chip. All VSSQ pins are connected in chip.
- 12 -
Rev. 1.3 (Jul. 2002)
K4D263238D
AC CHARACTERISTICS
Parameter
CK cycle time CK high level width CK low level width DQS out access time from CK Output access time from CK Data strobe edge to Dout edge Read preamble Read postamble CK to valid DQS-in DQS-In setup time DQS-in hold time DQS write postamble DQS-In high level width DQS-In low level width Address and Control input setup Address and Control input hold DQ and DM setup time to DQS DQ and DM hold time to DQS Clock half period Data output hold time from DQS CL=3 CL=4
128M DDR SDRAM
Symbol
-40 Min
4.0 0.45 0.45 -0.6 -0.6 0.9 0.4 0.85 0 0.35 0.4 0.4 0.4 0.9 0.9 0.4 0.4 tCLmin or tCHmin tHP-0.4
-50 Max
8 0.55 0.55 0.6 0.6 0.4 1.1 0.6 1.15 0.6 0.6 0.6 -
Min
5.0 0.45 0.45 -0.7 -0.7 0.9 0.4 0.8 0 0.25 0.4 0.4 0.4 1.0 1.0 0.45 0.45 tCLmin or tCHmin tHP-0.45
Max
10 0.55 0.55 +0.7 +0.7 +0.45 1.1 0.6 1.2 0.6 0.6 0.6 -
Unit
ns ns tCK tCK ns ns ns tCK tCK tCK ns tCK tCK tCK tCK ns ns ns ns ns ns
Note
tCK tCH tCL tDQSCK tAC tDQSQ tRPRE tRPST tDQSS tWPRES tWPREH tWPST tDQSH tDQSL tIS tIH tDS tDH tHP tQH
1
1 1
Simplified Timing @ BL=2, CL=3
tCH tCK
tCL
0 CK, CK
1
2
3
4
5
6
7
8
CS
tDQSCK
tIS tIH tDQSS tDQSH tWPST
DQS
tRPRE
tRPST
tWPREH tWPRES
tDS tDH
Hi-Z
tDQSQ tAC
DQ
Da1
Da2
Db0
Db1
Hi-Z
DM
COMMAND READA
WRITEB
- 13 -
Rev. 1.3 (Jul. 2002)
K4D263238D
128M DDR SDRAM
Note 1 : - The JEDEC DDR specification currently defines the output data valid window(tDV) as the time period when the data strobe and all data associated with that data strobe are coincidentally valid. - The previously used definition of tDV(=0.35tCK) artificially penalizes system timing budgets by assuming the worst case output valid window even then the clock duty cycle applied to the device is better than 45/55% - A new AC timing term, tQH which stands for data output hold time from DQS is defined to account for clock duty cycle variation and replaces tDV - tQHmin = tHP-X where . tHP=Minimum half clock period for any given cycle and is defined by clock high or clock low time(tCH,tCL) . X=A frequency dependent timing allowance account for tDQSQmax
tQH Timing (CL3, BL2)
tHP 0 CK, CK 1 2 3 4 5
CS
DQS tDQSQ(max) tQH tDQSQ(max) DQ
Da0 Da1
COMMAND
READA
- 14 -
Rev. 1.3 (Jul. 2002)
K4D263238D
AC CHARACTERISTICS (I)
Parameter
Row cycle time Refresh row cycle time Row active time RAS to CAS delay for Read RAS to CAS delay for Write Row precharge time Row active to Row active Last data in to Row precharge Last data in to Read command Col. address to Col. address Mode register set cycle time Auto precharge write recovery + Precharge Exit self refresh to read command Power down exit time Refresh interval time
128M DDR SDRAM
-40 Min
15 17 10 5 3 5 3 3 2 1 2 8 200
1tCK+tIS
Symbol
-50 Max
100K -
Min
12 14 8 4 2 4 2 2 2 1 2 6 200
1tCK+tIS
Max
100K -
Unit
Note
tRC tRFC tRAS tRCDRD tRCDWR tRP tRRD tWR tCDLR tCCD tMRD
tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK ns us
1 1
tDAL
tXSR tPDEX tREF
7.8
-
7.8
-
Note :1 For normal write operation, even numbers of Din are to be written inside DRAM
- 15 -
Rev. 1.3 (Jul. 2002)
K4D263238D
AC CHARACTERISTICS (II)
K4D263238D-QC40 Frequency Cas Latency 250MHz ( 4.0ns ) 4 200MHz ( 5.0ns ) 3
128M DDR SDRAM
(Unit : Number of Clock)
tRC 15 12
tRFC 17 14
tRAS 10 8
tRCDRD tRCDWR 5 3 4 2
tRP 5 4
tRRD 3 2
tDAL 8 6
Unit
tCK tCK
K4D623238F-QC50 Frequency Cas Latency 200MHz ( 5.0ns ) 3 183MHz ( 5.5ns ) 3 166MHz ( 6.0ns ) 3
tRC 12 12 10
tRFC 14 14 12
tRAS 8 8 7
tRCDRD tRCDWR 4 2 4 2 3 2
tRP 4 4 3
tRRD 2 2 2
tDAL 6 6 5
Unit
tCK tCK tCK
* 183/166MHz were supported in K4D263238D-QC50
- 16 -
Rev. 1.3 (Jul. 2002)
K4D263238D
Simplified Timing(2) @ BL=4, CL=3
0
CK, CK
128M DDR SDRAM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
BA[1:0]
BAa
BAa
BAa
BAa
BAb
BAa
BAb
A8/AP
Ra Ra Ca
Ra
Rb
ADDR (A0~A7, A9~,A11)
Ra
Rb
Ca
Cb
WE
DQS
DQ
Da0 Da1 Da2 Da3
Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3
DM
COMMANDACTIVEA
WRITEA tRCD tRAS tRC
PRECH tRP
ACTIVEA
ACTIVEB
WRITEA
WRITEB
tRRD
Normal Write Burst (@ BL=4)
Multi Bank Interleaving Write Burst (@ BL=4)
- 17 -
Rev. 1.3 (Jul. 2002)
K4D263238D
PACKAGE DIMENSIONS (TQFP)
128M DDR SDRAM
Dimensions in Millimeters
0 ~ 7 17.20 0.20 14.00 0.10 #100 #1
23.20 0.20 20.00 0.10
0.575
0.825
0.30 0.08 0.13 MAX
0.65
0.09~0.20
1.00 0.10 1.20 MAX *
0.10 MAX
0.05 MIN 0.80 0.20
- 18 -
Rev. 1.3 (Jul. 2002)

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